rec.autos.simulators

I am running NASCAR in SVGA with digitized sound and all graphics set to auto
and it is incredibly smoooth. It really makes the game even more enjoyable than
it already was!! These board are new and just starting to appear in some of the
computer/games mags. You will definetly be hearing more about it.

I was somewhat skeptical when I ordered the board (no more expensive than
traditional boards) but I am very much sold now!

If anyone has any questions, feel free to write.

PS. for a distributor in your area, call the Manuf. at 818-339-8888

Hi.
Woah, 16 megs of 15ns cache memory?!?!  This is a typo, right?
Can you say expensive??!?    16megs of regular 70ns RAM is expensive enough,
let alone 15ns!  Besides, never heard of a cache being *that* large.  : )

Question:  I always thought that my 486dx50 connected with RAM at 50mhz,
not 8mhz.  I would think that the Pentium 100 accesses memory at least that
fast, as well.  Is this right?  8mhz is only for the ISA bus, right?  

But, we're still jealous of your system...   : )

Peace,
Omar F. Lari

Thanx for the reply. I was probably mis-reading the information  I have. However,
Softwin Reports, and independent lab, writes: (regarding ram access versus
P100)" the average access times for the EDRAM DX4-100 are significantly
faster as well- even at 32 bit data widths. At 16bits, the DX4-100 EDRAM
system offers twice the average memory access speed as the Pentium system
(10ns vs 20ns)

Avg: Read Operations (in Nanoseconds)

        DCA/2 dx4/100   Intel P100
8bit    19.47           20.49
16bit   18.76           20.34
32bit   28.4            30.28

Avg Write Operations (Nanoseconds)
8bit    30.9            102.08
16bit   30.34           101.27
32bit   29.79           100.62

From Softwin Reports 11/94
Hope this helps

Yeah, I htink it'll slow the frame speed down to about 0 fps.  SVGA consumes
a lot more memory just compute all of the pixels, and 4MB ain't enough to
even fit, let alone go fast.

--

Brian Wong                              Product Marketing Engineering

--

Brian Wong                              Product Marketing Engineering

   I always thought that the 50MHz (or 66 or 100) was internal speed of
the processor. I read (a long time ago though) that the bus frequency is
much lower as well as the DMA bus.

That's what I thought.
I could be wrong.

Dave.

Well, in a sense you're both right, & wrong !

You have to split up the parts of a PC into some components. The
memory *acutal SIMM boards* runs *usually* at the overall speed of
the motherboard. So, a DX33 memory bus would run at 33MHz, a DX50 at
50 Mhz etc. etc. There are some exceptions caused by clock doubling.
A DX2-66 motherboard runs at 33MHz, thus so does the memory bus. The
only memory than runs at 66MHz here is the 8Kb internal cache that
the processor has.

Just to complicate matters, there are some physical limits
involved. Generally, it has proved impossible (read v. expensive)
to try and run existing motherboard designs at more than 60 or so
MHz. Most of the Pentium 90 & 100MHz boards employ a further trick

and the processor support chipset is itself clock multiplied by 1.5
to get 90 MHz !!

The expansion slots are controlled by a second controller chip
which runs at a completely different and *independent* speed to the
rest of the machine (except in the case of VLB). The original IBM

The small VLB extensions on the end of your ISA slots, are actually
just extensions of some of the processor's address and control
lines. This means that they run at the external speed of the chip.

PCI is an entirely different design. It's known as a mezzanine bus.
The practical upshot of which, is that it sits between the processor
and *ALL* other devices in the PC (including memory - although it
has a separate data pathway). PCI runs at a constant 33MHz speed
with 32-bit data transfers - regardless of processor type & speed.

Generally speaking, memory & motherboard technology has so far not
kept pace with the processors - hence the complex second-level
cache designs, DMA snooping etc. that our PC's our doing these days
without us even knowing.

I'm keen to learn more about the motherboard that started this
thread... It might make my copy of ICR run a little faster :-)

Hope this clears up some of your queries - and helps you guys to
buy the right product !

Cheers...

=================================================================
    _/_/_/ _/ _/ _/ _/_/_/ :  Mike Fisher - Belmin Purchasing
  _/_/_/  _/ _/_/  _/_/    :                Systems Ltd. UK.
 _/  _/  _/ _/ _/ _/_/_/   :
=================================================================

  Wow! Thanks for the info. Anybody else out there who knows some or a
lot about the AMD's I'd very thankful to receive information of any kind.
  So Mike, basically, speaking of the PCI bus, you could have 400MHz
Pentium with some PCI bus cards. While the processor would run at 400MHz
(being cooled down with liquid Oxygen) the PCI data transfer would still
be 33MHz no matter what. Is that right? If that is right, then logically
concluded, PCI's don't have a very good future. Don't you think so too, guys?
  I hope I'm wrong though.

Dave.

   Is the memory access speed synchronized with the clock speed of the board?
What would the optimum access time of the RAM be versus the clock speed?

Hope this question makes sense.

Dave.

I'm pretty sure that the clock speed of the CPU is related to the bus
speed (i.e. a 486DX 33 accesses the bus at 33 Mhz.)

However, a clock doubled or tripled CPU  (486DX2/66 or 486DX4/100) don't.
They access it at the original speed before doubling/tripling (25 or 33 Mhz)

 - Rich

Rich Williams - Case Western Reserve University

--------------------------------------------------------------------
"At least you weren't named after some***in a book."
                           - Jenness Mceachran

Yes Dave, it does make sense, it goes something like this:

Memory speed is calibrated in nanoseconds. (Millionths of a second)
You may have seen things like "1Mb x 9 60ns SIMM". This describes
the time it takes the memory chip to 'refresh' between data
requests. So if the processor requests a byte, it will take 60ns
before the chip is ready to provide the next one.

Consider a motherboard running at 33MHz, fitted with 60ns SIMMS.
This means the processor gets one clock tick (ie. executes one
instruction in the case of a 486DX) every 0.0000000303 seconds. A
ram chip on the SIMM would take 0.000006 seconds to recover between
data requests. The numbers may look small, but check out the
number of zeroes. The processor in theory could wait for around
1000 ticks between bytes - just picking it's nose ! :-)

That's where cache memory and something called 'memory
interleaving' comes in. Cache is a very high-speed block of memory
placed in between the processor and the main memory. It gets on
with the job of retrieving data from main memory whilst the
processor is doing something else. (Some instructions can take
much longer than one 'tick' to execute.)

Memory interleaving is a neat little trick employed by
motherboards. It stores byte 1 in chip 1, byte 2 in chip 2, byte 3
in chip 3 .... and so on. The advantage of that is, if the
processor asks for several bytes in succession (as they usually do)
each chip gives up it's byte in turn - no refresh time to wait
for. Hopefully, by the time you've come round full circle, and need
another byte from chip 1, it will have refreshed.

Hope I'm not boring you guys - just love answering these questions.

See ya..

=================================================================
    _/_/_/ _/ _/ _/ _/_/_/ :  Mike Fisher - Belmin Purchasing
  _/_/_/  _/ _/_/  _/_/    :                Systems Ltd. UK.
 _/  _/  _/ _/ _/ _/_/_/   :
=================================================================

A nanosecond (ns) is 10e-9 seconds, hence your figure for access
time should be 0.00000006, less than a factor of two slower than the
CPU clock cycle time. So, when the CPU asks the memory for data it
has to wait just less than two clock cycles for the data to be
returned (assuming a perfect system, and no cache memory). So, for
the clock cycle where the CPU is waiting for the data, it goes into
what is known as a 'wait state' effectively doing nothing.  

If a byte is requested by the CPU which is not on the cache, the    
cache controller will access the main memory for the data, and when
it is received will pass it on to the CPU and update a line in the
cache RAM. During this period, the CPU goes into wait state whilst
waiting for the data to arrive. Once the data is on the cache
however, the CPU can access it much quicker, usually without any
wait states.

Cache controllers also have a feature called 'Burst Mode' which if
supported by the motherboard can be very useful. What happens is that
if a certain byte is requested by the CPU, the cache controller will
update a whole line of the cache in one go (16, 32 or 64 bytes). This
is efficient as the next byte the CPU requests is very likely to be
the next one in memory, which will hopefully already be on the cache
via the data burst.

This was not intended as a flame, just a friendly correction.

Andy.