>> Is the memory access speed synchronized with the clock speed of the
board?
>>What would the optimum access time of the RAM be versus the clock speed?
>>Hope this question makes sense.
>>Dave.
>Yes Dave, it does make sense, it goes something like this:
>Memory speed is calibrated in nanoseconds. (Millionths of a second)
>You may have seen things like "1Mb x 9 60ns SIMM". This describes
>the time it takes the memory chip to 'refresh' between data
>requests. So if the processor requests a byte, it will take 60ns
>before the chip is ready to provide the next one.
>Consider a motherboard running at 33MHz, fitted with 60ns SIMMS.
>This means the processor gets one clock tick (ie. executes one
>instruction in the case of a 486DX) every 0.0000000303 seconds. A
>ram chip on the SIMM would take 0.000006 seconds to recover between
>data requests. The numbers may look small, but check out the
>number of zeroes. The processor in theory could wait for around
>1000 ticks between bytes - just picking it's nose ! :-)
>That's where cache memory and something called 'memory
>interleaving' comes in. Cache is a very high-speed block of memory
>placed in between the processor and the main memory. It gets on
>with the job of retrieving data from main memory whilst the
>processor is doing something else. (Some instructions can take
>much longer than one 'tick' to execute.)
>Memory interleaving is a neat little trick employed by
>motherboards. It stores byte 1 in chip 1, byte 2 in chip 2, byte 3
>in chip 3 .... and so on. The advantage of that is, if the
>processor asks for several bytes in succession (as they usually do)
>each chip gives up it's byte in turn - no refresh time to wait
>for. Hopefully, by the time you've come round full circle, and need
>another byte from chip 1, it will have refreshed.
>Hope I'm not boring you guys - just love answering these questions.
>See ya..
like NASCAR. 16megs of 15ns cache can transfer information at 4 times the
speed of 60ns ram. Right?