Read from our cool affiliate CoolInfo on Intel's new .18 micron technology.
Intel Corp. came to the 44th International Electron Devices Meeting with a description of the
0.18-micron process it will take into volume production next year with its Katmai processor.
The delay per stage was reported to be less than 11 picoseconds at 1.5 V, which Intel claims
is the best reported in the literature to date for a 0.18-micron process. The process was
designed for operating voltages of 1.3 to 1.5 volts. And instead of using copper, the company
is sticking wiht aluminum wiring, for now. Eschewing copper, Intel chose to stick with
aluminum wiring, but adopted a fluorided silicon oxide (SiO2F) material for the inter-level-
dielectric. By adding 5.5 percent fluoride to silicon dioxide, the ILD has a k value of 3.55,
compared with 4.1 for Intel's previous SiO2-based ILD.
By using the lower-k dielectric, and pushing the aspect ratio (height vs. width) of the metal
lines to reduce the resistance of the narrowly spaced lines, Intel claims that its 0.18-
micron technology is faster than IBM Corp.'s copper-based process, and at lower process
costs. A test-vehicle chip created with the process-a 16-Mbit SRAM with more than 100 million
transistors-operates at 900 MHz. The SRAM cell takes up 5.9 square microns per six-transistor
cell, an indicator of the area required to eventually put large amounts of cache on the same
die as the processing core.
The 0.18-micron process "is poised to go into volume production in the next few quarters,"
said Simon Yang, the Intel engineer who presented the paper at IEDM. The Intel process-
development group was able to achieve a 130-nm physical gate length for the NMOS device, and
150 nm for the PMOS transistors. Intel has gone to more aggressive gate-length scaling. Mark
Bohr, director of process architecture and integration at Intel's site at Hillsboro, Ore.,
said that at the 0.35-micron technology node the gate length also was 0.35 micron; at the
0.25-micron generation (as defined by the Semiconductor Industry Association's road map), the
gate length was "close to 0.2," and in the 0.18-micron generation the gate length was scaled
to 0.13 micron.
Rather than shift to copper interconnects and a dual-damascene process, Intel chose to put
its energies into figuring out how to create the "tall and skinny" wires that can be spaced
far enough apart to avoid capacitive coupling, and yet with enough metal to reduce the
resistance that plagues thin wires.
Could you be more specific? LOL :)
jk
Andrew B.
San Diego
Wow that is neat... but it didn't say anything about a p2 900, only 900 mhz
sram.
rob.
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