NASCAR: Smooth SVGA!

I just upgraded my syetem and though I would share the great result with other sim fans. I upgraded from an ISA DX2/66 with 8 meg ram and Tseng4000 video to the new Ocean Systems Dynaimc Cache DCA-2 motherboard with an AMD DX4/100, Stealth 64 DRAM, VL Eide controller and Teac quad speed CD. This system utilizes a new type of 15ns memory system. It has 16meg of 15ns cache that allows the CPU to communicate with ram at CPU speed upto 88mhz! Even a Pentium 100 has to talk to the ram at 8mhz. The difference really shines in large programs that are memory intensive and or run in protected mode(like NASCAR, DOOM Etc..). I am running NASCAR in SVGA with digitized sound and all graphics set to auto and it is incredibly smoooth. It really makes the game even more enjoyable than it already was!! These board are new and just starting to appear in some of the computer/games mags. You will definetly be hearing more about it. I was somewhat skeptical when I ordered the board (no more expensive than traditional boards) but I am very much sold now! If anyone has any questions, feel free to write. PS. for a distributor in your area, call the Manuf. at 818-339-8888

Ragsdale) writes: >>I just upgraded my syetem and though I would share the great result with other >>sim fans. I upgraded from an ISA DX2/66 with 8 meg ram and Tseng4000 video >>to the new Ocean Systems Dynaimc Cache DCA-2 motherboard with an AMD >>DX4/100, Stealth 64 DRAM, VL Eide controller and Teac quad speed CD. This >>system utilizes a new type of 15ns memory system. It has 16meg of 15ns cache >>that allows the CPU to communicate with ram at CPU speed upto 88mhz! Even Thanx for the reply. I was probably mis-reading the information I have. However, Softwin Reports, and independent lab, writes: (regarding ram access versus P100)" the average access times for the EDRAM DX4-100 are significantly faster as well- even at 32 bit data widths. At 16bits, the DX4-100 EDRAM system offers twice the average memory access speed as the Pentium system (10ns vs 20ns) Avg: Read Operations (in Nanoseconds) DCA/2 dx4/100 Intel P100 8bit 19.47 20.49 16bit 18.76 20.34 32bit 28.4 30.28 Avg Write Operations (Nanoseconds) 8bit 30.9 102.08 16bit 30.34 101.27 32bit 29.79 100.62 From Softwin Reports 11/94 Hope this helps >>large programs that are memory intensive and or run in protected mode(like >>NASCAR, DOOM Etc..). >>I am running NASCAR in SVGA with digitized sound and all graphics set to auto >>and it is incredibly smoooth. It really makes the game even more enjoyable than >>it already was!! These board are new and just starting to appear in some of the

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>>computer/games mags. You will definetly be hearing more about it. >>I was somewhat skeptical when I ordered the board (no more expensive than >>traditional boards) but I am very much sold now! >>If anyone has any questions, feel free to write. >>PS. for a distributor in your area, call the Manuf. at 818-339-8888 >-- >Brian Wong Product Marketing Engineering

[stuff deleted] -------------end of quoted material------------------------------------------- Hi. Woah, 16 megs of 15ns cache memory?!?! This is a typo, right? Can you say expensive??!? 16megs of regular 70ns RAM is expensive enough, let alone 15ns! Besides, never heard of a cache being *that* large. : ) Question: I always thought that my 486dx50 connected with RAM at 50mhz, not 8mhz. I would think that the Pentium 100 accesses memory at least that fast, as well. Is this right? 8mhz is only for the ISA bus, right? But, we're still jealous of your system... : ) Peace, Omar F. Lari

I have finally got sound to work on my Nascar racing by Papyrus, but it is only the promo music at the beginning and the ending music befor exiting. There are no racing sounds. Any suggestions? Also if you have your sound card selected ie 16 SB, do you have to have a MIDI to work? One final question, I have SVGA but I haven't tried it out with the game yet. If I only have 4meg RAM and I use SVGA will this slow down the frame speed? Thanks for any and all help. -- *********************************************************************************Todd's world, home of Bucky the rat, Brewers, Brats, Beer, and Bucks. ********************************************************************************

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>I just upgraded my syetem and though I would share the great result with other >sim fans. I upgraded from an ISA DX2/66 with 8 meg ram and Tseng4000 video >to the new Ocean Systems Dynaimc Cache DCA-2 motherboard with an AMD >DX4/100, Stealth 64 DRAM, VL Eide controller and Teac quad speed CD. This >system utilizes a new type of 15ns memory system. It has 16meg of 15ns cache >that allows the CPU to communicate with ram at CPU speed upto 88mhz! Even >a Pentium 100 has to talk to the ram at 8mhz. The difference really shines in

I'm not disagreeing with your results, but most Pentiums have a private memory interface and do *NOT* talk to memory at 8Mz. (In fact, I have never heard of a Pentium that did.) The ISA bus is 8 Mhz and 16 bit or two bytes wide, so max theoretical speed is a bit over 16 MB/sec and in practice you can never see that due to residency, protocol overhead, etc. P90's require memory bandwidth of around 65 MB/sec just to keep running, and most designs provide something approaching this. -- Brian Wong Product Marketing Engineering

>I have finally got sound to work on my Nascar racing by Papyrus, but it is >only the promo music at the beginning and the ending music befor exiting. >There are no racing sounds. Any suggestions? Also if you have your sound I had this problem, I fixed it by seeting my DMA channel to 5. The only reason I knew to do that was because I had to do it to make the crash sounds work in IndyCar.... Yeah, I htink it'll slow the frame speed down to about 0 fps. SVGA consumes a lot more memory just compute all of the pixels, and 4MB ain't enough to even fit, let alone go fast. -- Brian Wong Product Marketing Engineering

Ragsdale) writes: >[stuff deleted] >>It has 16meg of 15ns cache that allows the CPU to communicate with ram at >>CPU speed upto 88mhz! Even a Pentium 100 has to talk to the ram at 8mhz. The

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>>difference really shines in large programs that are memory intensive and or >>run in protected mode (like NASCAR, DOOM Etc..). >-------------end of quoted material------------------------------------------- >Hi. >Woah, 16 megs of 15ns cache memory?!?! This is a typo, right? >Can you say expensive??!? 16megs of regular 70ns RAM is expensive

enough,

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>let alone 15ns! Besides, never heard of a cache being *that* large. : ) >Question: I always thought that my 486dx50 connected with RAM at 50mhz, >not 8mhz. I would think that the Pentium 100 accesses memory at least that >fast, as well. Is this right? 8mhz is only for the ISA bus, right? >But, we're still jealous of your system... : )

Actually, it's not any more expensive than traditional ram. Memory for the board is sold in 8meg modules. Each module consists of 8megs of ram and 8 megs of 15ns cache. Each module is around $350, about what traditional ram is going for.

I always thought that the 50MHz (or 66 or 100) was internal speed of the processor. I read (a long time ago though) that the bus frequency is much lower as well as the DMA bus. That's what I thought. I could be wrong. Dave.

Well, in a sense you're both right, & wrong ! You have to split up the parts of a PC into some components. The memory *acutal SIMM boards* runs *usually* at the overall speed of the motherboard. So, a DX33 memory bus would run at 33MHz, a DX50 at 50 Mhz etc. etc. There are some exceptions caused by clock doubling. A DX2-66 motherboard runs at 33MHz, thus so does the memory bus. The only memory than runs at 66MHz here is the 8Kb internal cache that the processor has. Just to complicate matters, there are some physical limits involved. Generally, it has proved impossible (read v. expensive) to try and run existing motherboard designs at more than 60 or so MHz. Most of the Pentium 90 & 100MHz boards employ a further trick and the processor support chipset is itself clock multiplied by 1.5 to get 90 MHz !! The expansion slots are controlled by a second controller chip which runs at a completely different and *independent* speed to the rest of the machine (except in the case of VLB). The original IBM The small VLB extensions on the end of your ISA slots, are actually just extensions of some of the processor's address and control lines. This means that they run at the external speed of the chip. PCI is an entirely different design. It's known as a mezzanine bus. The practical upshot of which, is that it sits between the processor and *ALL* other devices in the PC (including memory - although it has a separate data pathway). PCI runs at a constant 33MHz speed with 32-bit data transfers - regardless of processor type & speed. Generally speaking, memory & motherboard technology has so far not kept pace with the processors - hence the complex second-level cache designs, DMA snooping etc. that our PC's our doing these days without us even knowing. I'm keen to learn more about the motherboard that started this thread... It might make my copy of ICR run a little faster :-) Hope this clears up some of your queries - and helps you guys to buy the right product ! Cheers... ================================================================= _/_/_/ _/ _/ _/ _/_/_/ : Mike Fisher - Belmin Purchasing _/_/_/ _/ _/_/ _/_/ : Systems Ltd. UK. _/ _/ _/ _/ _/ _/_/_/ : =================================================================

<snip> <snip> Wow! Thanks for the info. Anybody else out there who knows some or a lot about the AMD's I'd very thankful to receive information of any kind. So Mike, basically, speaking of the PCI bus, you could have 400MHz Pentium with some PCI bus cards. While the processor would run at 400MHz (being cooled down with liquid Oxygen) the PCI data transfer would still be 33MHz no matter what. Is that right? If that is right, then logically concluded, PCI's don't have a very good future. Don't you think so too, guys? I hope I'm wrong though. Dave.

<snip> <snip> Is the memory access speed synchronized with the clock speed of the board? What would the optimum access time of the RAM be versus the clock speed? Hope this question makes sense. Dave.

I'm pretty sure that the clock speed of the CPU is related to the bus speed (i.e. a 486DX 33 accesses the bus at 33 Mhz.) However, a clock doubled or tripled CPU (486DX2/66 or 486DX4/100) don't. They access it at the original speed before doubling/tripling (25 or 33 Mhz) - Rich Rich Williams - Case Western Reserve University -------------------------------------------------------------------- "At least you weren't named after some***in a book." - Jenness Mceachran

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>Well, in a sense you're both right, & wrong ! >You have to split up the parts of a PC into some components. The >memory *acutal SIMM boards* runs *usually* at the overall speed of >the motherboard. So, a DX33 memory bus would run at 33MHz, a DX50 at >50 Mhz etc. etc. There are some exceptions caused by clock doubling. >A DX2-66 motherboard runs at 33MHz, thus so does the memory bus. The >only memory than runs at 66MHz here is the 8Kb internal cache that >the processor has. >Just to complicate matters, there are some physical limits >involved. Generally, it has proved impossible (read v. expensive) >to try and run existing motherboard designs at more than 60 or so >MHz. Most of the Pentium 90 & 100MHz boards employ a further trick >and the processor support chipset is itself clock multiplied by 1.5 >to get 90 MHz !! >The expansion slots are controlled by a second controller chip >which runs at a completely different and *independent* speed to the >rest of the machine (except in the case of VLB). The original IBM >The small VLB extensions on the end of your ISA slots, are actually >just extensions of some of the processor's address and control >lines. This means that they run at the external speed of the chip. >PCI is an entirely different design. It's known as a mezzanine bus. >The practical upshot of which, is that it sits between the processor >and *ALL* other devices in the PC (including memory - although it >has a separate data pathway). PCI runs at a constant 33MHz speed >with 32-bit data transfers - regardless of processor type & speed. >Generally speaking, memory & motherboard technology has so far not >kept pace with the processors - hence the complex second-level >cache designs, DMA snooping etc. that our PC's our doing these days >without us even knowing. >I'm keen to learn more about the motherboard that started this >thread... It might make my copy of ICR run a little faster :-) >Hope this clears up some of your queries - and helps you guys to >buy the right product ! >Cheers...

Thanks for the info. I posted the original article talking about how smooth my new EDRAM motherboard is able to run NASCAR in SVGA with all graphics on. IT is manufactured by Ocean Information Systems in Covina, CA. 818-339-8888. If you have any questions about it, let me know by Email. Take Care.....

>> Is the memory access speed synchronized with the clock speed of the board?

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>>What would the optimum access time of the RAM be versus the clock speed? >>Hope this question makes sense. >>Dave. >Yes Dave, it does make sense, it goes something like this: >Memory speed is calibrated in nanoseconds. (Millionths of a second) >You may have seen things like "1Mb x 9 60ns SIMM". This describes >the time it takes the memory chip to 'refresh' between data >requests. So if the processor requests a byte, it will take 60ns >before the chip is ready to provide the next one. >Consider a motherboard running at 33MHz, fitted with 60ns SIMMS. >This means the processor gets one clock tick (ie. executes one >instruction in the case of a 486DX) every 0.0000000303 seconds. A >ram chip on the SIMM would take 0.000006 seconds to recover between >data requests. The numbers may look small, but check out the >number of zeroes. The processor in theory could wait for around >1000 ticks between bytes - just picking it's nose ! :-) >That's where cache memory and something called 'memory >interleaving' comes in. Cache is a very high-speed block of memory >placed in between the processor and the main memory. It gets on >with the job of retrieving data from main memory whilst the >processor is doing something else. (Some instructions can take >much longer than one 'tick' to execute.) >Memory interleaving is a neat little trick employed by >motherboards. It stores byte 1 in chip 1, byte 2 in chip 2, byte 3 >in chip 3 .... and so on. The advantage of that is, if the >processor asks for several bytes in succession (as they usually do) >each chip gives up it's byte in turn - no refresh time to wait >for. Hopefully, by the time you've come round full circle, and need >another byte from chip 1, it will have refreshed. >Hope I'm not boring you guys - just love answering these questions. >See ya..

I guess that's why the EDRAM based system performs so well with programs like NASCAR. 16megs of 15ns cache can transfer information at 4 times the speed of 60ns ram. Right?

Yes Dave, it does make sense, it goes something like this: Memory speed is calibrated in nanoseconds. (Millionths of a second) You may have seen things like "1Mb x 9 60ns SIMM". This describes the time it takes the memory chip to 'refresh' between data requests. So if the processor requests a byte, it will take 60ns before the chip is ready to provide the next one. Consider a motherboard running at 33MHz, fitted with 60ns SIMMS. This means the processor gets one clock tick (ie. executes one instruction in the case of a 486DX) every 0.0000000303 seconds. A ram chip on the SIMM would take 0.000006 seconds to recover between data requests. The numbers may look small, but check out the number of zeroes. The processor in theory could wait for around 1000 ticks between bytes - just picking it's nose ! :-) That's where cache memory and something called 'memory interleaving' comes in. Cache is a very high-speed block of memory placed in between the processor and the main memory. It gets on with the job of retrieving data from main memory whilst the processor is doing something else. (Some instructions can take much longer than one 'tick' to execute.) Memory interleaving is a neat little trick employed by motherboards. It stores byte 1 in chip 1, byte 2 in chip 2, byte 3 in chip 3 .... and so on. The advantage of that is, if the processor asks for several bytes in succession (as they usually do) each chip gives up it's byte in turn - no refresh time to wait for. Hopefully, by the time you've come round full circle, and need another byte from chip 1, it will have refreshed. Hope I'm not boring you guys - just love answering these questions. See ya.. ================================================================= _/_/_/ _/ _/ _/ _/_/_/ : Mike Fisher - Belmin Purchasing _/_/_/ _/ _/_/ _/_/ : Systems Ltd. UK. _/ _/ _/ _/ _/ _/_/_/ : =================================================================

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>> Is the memory access speed synchronized with the clock speed of the board? >>What would the optimum access time of the RAM be versus the clock speed? > Yes Dave, it does make sense, it goes something like this: > Memory speed is calibrated in nanoseconds. (Millionths of a second) > You may have seen things like "1Mb x 9 60ns SIMM". This describes > the time it takes the memory chip to 'refresh' between data > requests. So if the processor requests a byte, it will take 60ns > before the chip is ready to provide the next one.

Memory is not calibrated to a time at all. The access time of a chip (usually 60-70ns in the case of PCs) is the time it takes for the memory chip (or chips in the case of a SIMM) to put the data requested by the CPU onto the data bus. A nanosecond (ns) is 10e-9 seconds, hence your figure for access time should be 0.00000006, less than a factor of two slower than the CPU clock cycle time. So, when the CPU asks the memory for data it has to wait just less than two clock cycles for the data to be returned (assuming a perfect system, and no cache memory). So, for the clock cycle where the CPU is waiting for the data, it goes into what is known as a 'wait state' effectively doing nothing. If a byte is requested by the CPU which is not on the cache, the cache controller will access the main memory for the data, and when it is received will pass it on to the CPU and update a line in the cache RAM. During this period, the CPU goes into wait state whilst waiting for the data to arrive. Once the data is on the cache however, the CPU can access it much quicker, usually without any wait states. Cache controllers also have a feature called 'Burst Mode' which if supported by the motherboard can be very useful. What happens is that if a certain byte is requested by the CPU, the cache controller will update a whole line of the cache in one go (16, 32 or 64 bytes). This is efficient as the next byte the CPU requests is very likely to be the next one in memory, which will hopefully already be on the cache via the data burst. This was not intended as a flame, just a friendly correction. Andy.

blah blah blah blah blah <didn't wanna put the whole quote in here:)> Thanks for response. Now, I know there is at least two major types of memory chips: dynamic and static. I heard that static ram is WAAYYY faster than dynamic ram. Is that true or not? David Kadlcak ------------- Aerospace Engineering Programm ############################################################################# ## ## ## E m b r y - R i d d l e ## ## ## ## A e r o n a u t i c a l U n i v e r s i t y ## ## ## ## ## ## To Live Is To Die, ***************************** ## ## To Die Happy, * Michael Andretti in '95 * ## ## Is To Drink Beer. ***************************** ## ## ## ## =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= ## ## ## ## Pilnser Urquell <== Drink it 24-7 ==> Gambrinus ## ## ## #############################################################################

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>> Is the memory access speed synchronized with the clock speed of >> the board? What would the optimum access time of the RAM be >> versus the clock speed? >> >> Hope this question makes sense. >> >> Dave. >> >>

Mike> Yes Dave, it does make sense, it goes something like this: Mike> Consider a motherboard running at 33MHz, fitted with 60ns Mike> SIMMS. This means the processor gets one clock tick Mike> (ie. executes one instruction in the case of a 486DX) every Mike> 0.0000000303 seconds. A ram chip on the SIMM would take Mike> 0.000006 seconds to recover between data requests. The ^^^^^^^^^^^^ Of course this is 6 micro seconds which is 100 times bigger than the 60ns mentioned above. 60 ns is actually just 2 times larger than the processor clock period. And although instruction pipelining may play some role, rarely does an instruction on a CISC achitecture chip execute in 1 cycle. So the problem is not as extreme as suggested here. Mike> numbers may look small, but check out the number of Mike> zeroes. The processor in theory could wait for around 1000 Mike> ticks between bytes - just picking it's nose ! :-) [cache and interleaving descriptions deleted] Mike> Hope I'm not boring you guys - just love answering these Mike> questions. Mike> See ya.. Mike> ================================================================= Mike> _/_/_/ _/ _/ _/ _/_/_/ : Mike Fisher - Belmin Purchasing Mike> _/_/_/ _/ _/_/ _/_/ : Systems Ltd. UK. _/ _/ _/ _/ _/ Mike> _/_/_/ : Mike> ================================================================= -- +---------------------------------------------------------------+ |Jim Dibb | My car doesn't care if your | |Sr. Software Engineer | car climbed MT. WASHINGTON | |CLARiiON | | |Data General Corp. | | +---------------------------------------------------------------+

> I guess that's why the EDRAM based system performs so well with programs > like NASCAR. 16megs of 15ns cache can transfer information at 4 times the > speed of 60ns ram. Right? How much did you pay for your cache memory? 2 million dollars? David Kadlcak ------------- Aerospace Engineering Programm ############################################################################# ## ## ## E m b r y - R i d d l e ## ## ## ## A e r o n a u t i c a l U n i v e r s i t y ## ## ## ## ## ## To Live Is To Die, ***************************** ## ## To Die Happy, * Michael Andretti in '95 * ## ## Is To Drink Beer. ***************************** ## ## ## ## =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= ## ## ## ## Pilsner Urquell <== Drink it 24-7 ==> Gambrinus ## ## ## #############################################################################

[snip] Thanks Andy - my maths never were very good. Right in principal though ? ================================================================= _/_/_/ _/ _/ _/ _/_/_/ : Mike Fisher - Belmin Purchasing _/_/_/ _/ _/_/ _/_/ : Systems Ltd. UK. _/ _/ _/ _/ _/ _/_/_/ : =================================================================

>> >> like NASCAR. 16megs of 15ns cache can transfer information at 4 times the

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>> >> speed of 60ns ram. Right? >> > How much did you pay for your cache memory? 2 million dollars? >> No more expensive than traditional ram .8meg is about $350. > Can you use more than 512k of Cache or did you by SRAM SIMMs

somewhere? >IOW, did you put cache mem where regular RAM is supposed be? This board has special slots for the 15ns EDRAM. I have 16meg of cache and I believe the board will handle upto 32meg of 15ns cache.

[DRAM timing discussion deleted] I would disagree. The problem is much worse than suggested. In both RISC and CISC machines, the latency of any given instruction may be 5 or more clock cycles. A pipelined processor (all modern processors) masks this latency by executing an instruction in stages. By overlapping instructions in the pipeline, a total throughput of close to 1 instruction per clock cycle can be attained (superscalar processors with multiple pipelines, like the Pentium, can execute > 1 instruction/cc). Data dependencies, branches, and some specific instructions can stall the pipeline and will reduce throughput to less than 1 instruction/cc. However, with well-written code, a figure close to 1 (and certainly better than 0.5) can be maintained. Keep in mind that even though the external interface to most new Intel processors is 30-33Mhz, the processor executes instructions at full speed out of internal cache. As an example, if both the internal and external caches of a DX4/100 miss, a system with standard 70ns DRAM will cause the processor to wait for 70ns/10ns = 7 clock cycles (14% efficiency!). While certain DRAM access modes can help to somewhat alleviate this for contiguous memory accesses, the problem is very serious. As another example, while a 98% cache hit rate sounds pretty darn good... For a 100MHz processor with 70ns DRAM: A 98% hit rate yields 89% efficiency A 95% hit rate yields 77% efficiency A 90% hit rate yields 63% efficiency A 50% hit rate yields 25% efficiency! The efficiency falls off hyperbolically with cache hit rate. Small improvements to cache hit rate can dramatically increase system performance. Please understand that I am *not* implying that it is easy to increase hit rate beyond simply providing larger caches. My point is that memory hierarchy performance is *absolutely critical* to the overall performance of the computer. It is probably the single biggest bottleneck to the performance of almost all current computers and I doubt that the value of a good cache design can be overstated. Joe Thompson

At current cache prices of around $30 for 128K, that makes it about $240 per Meg. 16 Megs should have cost him close to $4,000! Wow it can be done, but with more money than most of us will ever see, or pay for a complete system. If he had it and spent $4,000 on memory, good for him and enjoy. Roman

:>> >> like NASCAR. 16megs of 15ns cache can transfer information at 4 times the :>> >> speed of 60ns ram. Right? :>> > :>> > :>> > How much did you pay for your cache memory? 2 million dollars? :>> :>> No more expensive than traditional ram. *meg is about $350. :>> :>> :> Can you use more than 512k of Cache or did you by SRAM SIMMs somewhere? :>IOW, did you put cache mem where regular RAM is supposed be? This is EDRAM they are talking about. More info in appropriate groups, I'm sure. Anssi

>At current cache prices of around $30 for 128K, that makes it about $240 per >Meg. 16 Megs should have cost him close to $4,000! Wow it can be done, but >with more money than most of us will ever see, or pay for a complete system. >If he had it and spent $4,000 on memory, good for him and enjoy. >Roman Hey! Smeghead! Try thinking before you jump down someones throat so publicly. Ever considered the possibility of setting up standard memory (RAM) as cache with a program as common as SmartDrive (Ug, I always hoped that I'd never mention this program). Cheers, Scott Cordon. -- Cheers, Scott Cordon

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>Subject: Re: NASCAR: Smooth SVGA! >Date: 2 Mar 1995 01:05:02 GMT >>At current cache prices of around $30 for 128K, that makes it about $240 per >>Meg. 16 Megs should have cost him close to $4,000! Wow it can be done, but >>with more money than most of us will ever see, or pay for a complete system. >>If he had it and spent $4,000 on memory, good for him and enjoy. >>Roman >Hey! Smeghead! Try thinking before you jump down someones throat so >publicly. Ever considered the possibility of setting up standard memory >(RAM) as cache with a program as common as SmartDrive (Ug, I always hoped >that I'd never mention this program). > Cheers, > Scott Cordon. >-- >Cheers, > Scott Cordon

------------------------------ Scott, seems like you're jumping into the thread without knowing the real topic. We're talking about 15ns SRAM (yes, 16 megs worth!), not about caching a harddrive. : ) Seems like there are awesome new developments in memory technology out there of which we aren't all aware...

Talk about the pot calling the kettle black. Craig

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>>Subject: Re: NASCAR: Smooth SVGA! >>Date: 2 Mar 1995 01:05:02 GMT >>>At current cache prices of around $30 for 128K, that makes it about $240

per >>>Meg. 16 Megs should have cost him close to $4,000! Wow it can be done, but >>>with more money than most of us will ever see, or pay for a complete system.

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>>>If he had it and spent $4,000 on memory, good for him and enjoy. >>>Roman >>Hey! Smeghead! Try thinking before you jump down someones throat so >>publicly. Ever considered the possibility of setting up standard memory >>(RAM) as cache with a program as common as SmartDrive (Ug, I always

hoped

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>>that I'd never mention this program). >> Cheers, >> Scott Cordon. >Scott, seems like you're jumping into the thread without >knowing the real topic. We're talking about 15ns SRAM (yes, >16 megs worth!), not about caching a harddrive. : ) >Seems like there are awesome new developments in memory technology >out there of which we aren't all aware... >8 ,egs of 15ns cache/ram is $320-350. I paid $700 for 16 meg of 15ns. I belive

the price may have come down even a little more in the last couple of weeks.

Which is? David Kadlcak ------------- Aerospace Engineering Student Embry-Riddle Aeronautical University Prescott Campus, Arizona =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-= ## To Live Is To Die, ***************************** ## ## To Die Happy, * Michael Andretti in '95 * ## ## Is To Drink Beer. ***************************** ## ## -- Vsude dobre, doma nejlip. V Plzni pivo prsi !!! ## =-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=